FinFET BASED ULTRA LOW POWER SRAM A project REPORT Submitted by JENY ELSA JOJI MGP16ECVE01 to the APJ Abdul Kalam Technological University in partial fulfillment of the requirements for the award of the degree of Master of Technology in Electronics


FinFET BASED ULTRA LOW POWER SRAM

A project REPORT Submitted by

JENY ELSA JOJI

MGP16ECVE01

to

the APJ Abdul Kalam Technological University in partial fulfillment of the requirements for the award of the degree

of

Master of Technology in
Electronics & Communication Engineering

(With Specialization in VLSI & Embedded Systems)

Department of Electronics & Communication Engineering SAINTGITS COLLEGE OF ENGINEERING Kottukulam Hills, Pathamuttom P.O, Kottayam 686 532

May, 2018

DECLARATION

I undersigned hereby declare that the project report “FinFET BASED ULTRA LOW POWER SRAM ” , submitted for partial fulfillment of the requirements for the award of degree of Master of Technology of the APJ Abdul Kalam Technological University, Kerala is a bonafide work done by me under supervision of Er. Sreekala K. S .This submission represents my ideas in my own words and where ideas or words of others have been included,I have adequately and accurately cited and referenced the original sources. I also declare that I have adhered to ethics of academic honesty and integrity and have not misrepresented or fabricated any data or idea or fact or source in my submission. I understand that any violation of the above will be a cause for disciplinary action by the institute and/or the University and can also evoke penal action from the sources which have thus not been properly cited or from whom proper permission has not been obtained. This report has not been previously formed the basis for the award of any degree, diploma or similar title of any other University.

Pathamuttom JENY ELSA JOJI MGP16ECVE01

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
SAINTGITS COLLEGE OF ENGINEERING
Kottukulam Hills, Pathamuttom P.O., Kottayam 686 532.

(Approved by AICTE and affiliated to APJ Abdul Kalam Technological University)

CERTIFICATE

This is to certify that the report entitled “FinFET BASED ULTRA LOW POWER SRAM ” submitted by “JENY ELSA JOJI, MGP16ECVE01” to the APJ Abdul Kalam Technological University in partial fulfillment of the requirements for the award of the Degree of Master of Technology in VLSI & Embedded Systems ( Electronics
& Communication Engineering) is a bonafide record of the project carried out by her under our guidance and supervision. This report in any form has not been submitted to
any other University or Institute for any purpose.

Er. Sreekala K. S
Internal Supervisor
Er. Marie Kottayil James
Project Co-ordinator

Dr. Ansal K. A
PG Co-ordinator
Dr. Riboy Cheriyan
Professor & HOD

ACKNOWLEDGEMENT

First and foremost, I thank God Almighty for his blessings and deliverance throughout the preparation of this thesis.

I take this opportunity to express sincere thanks to our principal Dr. M. D. Mathew
for all the facilities extended to accomplishing my goal.

I would also be grateful to Dr. Riboy Cheriyan, HOD of Electronics and Communi- cation Engineering, Dr. Ansal K. A, PG Co-ordinator and Er. Marie Kottayil James, Project Co-ordinator for their full support rendered during my thesis presentation.

I would like to extend my heartfelt gratitude towards my guide Er. Sreekala K. S, Assistant Professor, Department of Electronics and Communication Engineering, for her unparalleled guidance, relevant suggestions and motivations.

I hereby extend my sincere gratitude to all the staff members of the Electronics and
Communication Engineering Department for all the support given to me.

Last, but not the least, I extend my sincere thanks to my parents and friends for their valuable help and encouragement in my endeavour.

JENY ELSA JOJI

ABSTRACT

Scaling of conventional CMOS technology has been motivated by the need for higher integration density and performance over the last few decades. Static power consump- tion is a major concern when designing nano-scaled integrated circuits. In SRAM cells, where the contents must be retained for long durations with a constant power supply, the sub-threshold current is a significant source of power consumption. Therefore, when designing future SRAM cells for low power applications, a vital design objective is to minimize the sub-threshold current. FinFETs can be used as a suitable replacement to CMOS because of their low power consumption and sub-threshold leakage. These de- vices increase the controllability of gate on channel with respect to CMOS transistors and suppress the short channel effects (SCE). A new technique is proposed in order to design a low leakage SRAM cell which improves the cell characteristics in read, write and hold modes using the FinFET technology and it is observed that the read power is reduced by 39% and the write and hold power is reduced by 81% and 62% respectively when compared to the conventional FinFET SRAM. The proposed technique is also used to implement a 16 × 16 SRAM array using the Hspice software at 20nm technol- ogy.

Keywords: CMOS, FinFET, short channel effects, sub-threshold leakage, SRAM

CONTENTS

Contents Page No.

ACKNOWLEDGEMENT i ABSTRACT ii LIST OF TABLES v LIST OF FIGURES vi ABBREVIATIONS vii NOTATIONS viii Chapter 1: INTRODUCTION 1
1.1 PROBLEM DEFINITION . . . . . . . . . . . . . . . . . . . . . . 1
1.2 SCOPE OF THE PROJECT . . . . . . . . . . . . . . . . . . . . . 2
1.3 OBJECTIVES OF THE PROJECT . . . . . . . . . . . . . . . . . . 5
1.4 CONVENTIONAL FinFET SRAM . . . . . . . . . . . . . . . . . 5
1.4.1 HOLD MODE . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.2 READ MODE . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4.3 WRITE MODE . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 STATIC NOISE MARGIN (SNM) . . . . . . . . . . . . . . . . . . 6
1.5.1 SRAM READ STABILITY . . . . . . . . . . . . . . . . . . 6
1.5.2 SRAM WRITE STABILITY . . . . . . . . . . . . . . . . . 7
1.6 ORGANIZATION OF THE PROJECT . . . . . . . . . . . . . . . 7
1.7 SUMMARY OF THE PROJECT . . . . . . . . . . . . . . . . . . . 8

Chapter 2: LITERATURE REVIEW 9
2.1 SRAM with Power Gating Technique . . . . . . . . . . . . . . . . 9
2.2 SRAM with Current Sharing Concept . . . . . . . . . . . . . . . . 10
2.3 8T SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 7T SRAM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 3: SRAM WITH POWER REDUCTION TECHNIQUE 14
3.1 DIFFERENT OPERATING MODES . . . . . . . . . . . . . . . . 15
3.1.1 READ MODE . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2 WRITE MODE . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.3 HOLD MODE . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 4: 16 × 16 SRAM ARRAY 17
4.1 PRECHARGE CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 WRITE DRIVER CIRCUIT . . . . . . . . . . . . . . . . . . . . . 18
4.3 SENSE AMPLIFIER . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 ROW/COLUMN DECODER . . . . . . . . . . . . . . . . . . . . 20

Chapter 5: RESULTS AND DISCUSSION 23

Chapter 6: CONCLUSIONS 33

REFERENCES 35

LIST OF PUBLICATIONS 36

LIST OF TABLES

No. Title Page No.

2.1 SNM of 8T SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Power of 7T SRAM Array . . . . . . . . . . . . . . . . . . . . . . 12

3.1 State of Sleep Transistor at Different Operational Modes . . . . . . 15

4.1 Output Selection of the Decoder . . . . . . . . . . . . . . . . . . . 22

5.1 Power and Delay of Proposed Technique . . . . . . . . . . . . . . . 23
5.2 Comparison of SNM . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Comparison of Delay . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 Comparison of Static Power . . . . . . . . . . . . . . . . . . . . . 28
5.5 Variation of Power with Temperature . . . . . . . . . . . . . . . . . 28
5.6 Variation of Power with Threshold Voltage (VT H ) . . . . . . . . . . 29
5.7 Power of a 16 × 16 SRAM Array . . . . . . . . . . . . . . . . . . . 30
5.8 Comparison with Previous Works . . . . . . . . . . . . . . . . . . . 31

LIST OF FIGURES

No. Title Page No.

1.1 FinFET Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 FinFET Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Shorted Gate and Independent Gate FinFET Structure . . . . . . . . 4
1.4 FinFET SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Set Up for SNM Definition . . . . . . . . . . . . . . . . . . . . . . 7

2.1 SRAM with Power Gating Technique . . . . . . . . . . . . . . . . . 9
2.2 SRAM with Current Sharing Concept . . . . . . . . . . . . . . . . 10
2.3 8T SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 7T SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 SRAM with Power Reduction Technique . . . . . . . . . . . . . . . 14

4.1 Block Diagram of SRAM Architecture . . . . . . . . . . . . . . . . 17
4.2 Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Write driver circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Block Diagram of Decoder . . . . . . . . . . . . . . . . . . . . . . 21
4.6 Circuit Diagram of Decoder . . . . . . . . . . . . . . . . . . . . . . 21

5.1 Butterfly Curve of a SRAM Cell . . . . . . . . . . . . . . . . . . . 23
5.2 Butterfly Curve for Read SNM . . . . . . . . . . . . . . . . . . . . 24
5.3 Write Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4 Butterfly Curve for Hold SNM . . . . . . . . . . . . . . . . . . . . 25
5.5 Read Noise Margin of 6T SRAM . . . . . . . . . . . . . . . . . . . 25
5.6 Write Noise Margin of 6T SRAM . . . . . . . . . . . . . . . . . . 26
5.7 Hold Noise Margin of 6T SRAM . . . . . . . . . . . . . . . . . . . 26
5.8 Comparison of SNM . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.9 Comparison of Delay . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.10 Comparison of Static Power . . . . . . . . . . . . . . . . . . . . . 28
5.11 Variation of Power with Temperature . . . . . . . . . . . . . . . . . 29
5.12 Variation of Power with Threshold Voltage . . . . . . . . . . . . . . 29
5.13 Power of a 16 × 16 SRAM Array . . . . . . . . . . . . . . . . . . . 30
5.14 Comparison of Read Stability . . . . . . . . . . . . . . . . . . . . . 30
5.15 Comparison of Write Stability . . . . . . . . . . . . . . . . . . . . 31
5.16 Comparison of Hold Stability . . . . . . . . . . . . . . . . . . . . . 31

ABBREVIATIONS

CMOS COMPLEMENTORY METAL OXIDE SEMICONDUCTOR
FinFET FIN FIELD EFFECT TRANSISTOR
SNM STATIC NOISE MARGIN
SRAM STATIC RANDOM ACCESS MEMORY

NOTATIONS

HF in Height of the Fin TF in Width of the Fin VDD Supply Voltage
VT H Threshold voltage

CHAPTER 1
INTRODUCTION

Static Random Access Memory (SRAM) serves as cache memory, interfacing between DRAMs and the CPU as SRAM operates fast and consumes a less power during standby mode.SRAM is volatile memory which stores data in forms of binary ones and zeros. SRAM provides high-performance at low-power for the very large scale integration (VLSI) applications. SRAM has high performance with low power consumption dur- ing standby mode when compared to other memories.SRAM is volatile memory which stores data in forms of binary ones and zeros.

1.1 PROBLEM DEFINITION

Due to Moores law, the scaling of CMOS technology well is changed into the nanoscale regime. This shrinking increases the reliability issues in the design and leads to increase in short channel effects (SCEs)and leakage currents.This increases the power consump- tion of a SRAM cell and the cell stability is also affected.

Power dissipation in CMOS circuits can be categorized into two main components
– dynamic and static power dissipation. Dynamic dissipation occurs due to switch- ing transient current (referred to as short-circuit current) and charging and discharging of load capacitances (referred to as capacitive switching current). Static dissipation is due to leakage currents drawn continuously from the power supply (Verma et al.,
2015). There are various components which contribute to leakage current, such as sub- threshold leakage, reverse-biased PN junctions, drain-induced barrier lowering (DIBL), gate-induced drain leakage, punch through currents, gate oxide tunneling, and hot car- rier effects. The three main leakage components are: sub-threshold leakage, junction tunneling leakage and band to band tunneling.

The reversed biased p-n junction leakage has two main components: one is minority carriers diffusion near the edge of the depletion region and the other is due to electron- hole pair generation in the depletion region of the reverse biased junction. The junction tunneling current is an exponential function of junction doping and reverse bias voltage across the junction.Since junction tunneling current is a minimal contributor to the total leakage current, there is no need to reduce this component of leakage in an SRAM; however, it should be noticed that by applying a forward substrate biasing, junction tunneling current can be reduced .

Sub-threshold leakage is the drain-source current of a transistor when the gate- source voltage is less than the threshold voltage. More precisely, sub-threshold leak- age happens when the transistor is operating in the weak inversion region. The sub- threshold current depends exponentially on threshold voltage, which results in large sub-threshold current in short channel devices. To reduce the sub threshold leakage of an SRAM cell, one can increase the threshold voltage of all or some of the transistors in the cell (Cakici et al., 2007). The drawback of this technique is an increase in read/write delay of the cell. If the threshold voltage of the pull up PMOS transistors is increased, the write delay increases whereas the effect on the read delay would be negligible. On the other hand, if the threshold voltage of the pull down NMOS transistors is increased, the read delay increases whereas the effect on the write delay would be marginal. By increasing the threshold voltage of the pass transistors both read and write delays in- crease. Due to the delay of sense amplifiers and output buffers in a read path, the write delay of an SRAM cell tends to be smaller than its read delay. Therefore, one can think of reducing the sub threshold leakage by increasing the threshold voltage of the PMOS transistors as long as the write delay is less than the read delay.

The direct band to band tunneling model describes the carrier generation in high field region without any influence of local traps. The band to band tunneling process describes the field emission of valence electrons leaving back holes. At sufficient gate bias, band to band tunneling occurs when conduction band of intrinsic region aligns with valence band of p region.

1.2 SCOPE OF THE PROJECT

FinFET, a tri-gate transistor that has a thin silicon fin which acts as the conducting chan- nel and conducts the electrons between the drain and source can be used as a suitable replacement for CMOS. In FinFET the short-channel length effect can be controlled by reducing the off-state leakage (Lourts Deepak and Dhulipalla, 2013). FinFET are used to suppress the short channel effects and leakage currents.

FinFET, also known as Fin Field Effect Transistor is a non planar or “3D” transistor. The main feature of the FinFET is the conducting channel which is wrapped by the thin silicon “Fin”. It is introduced by Berkeley researchers of University of California. The effective length of the device is determined by the Fin thickness.Regarding its structure, it has a vertical Fin on the substrate that runs between the drain and source area and this is protruded as the Fin above the substrate (Farkhani et al., 2014). The FinFET model structure consists of following regions

• With very low doping silicon fin region.

• Poly-silicon region, source and drain contact region, highly doped.

• Gate region- oxide (SiO2)

The structure of FinFET is shown in Figure 1.1. For FinFET, the height of the Fin determines the width of the device. HF in and TF in are the Fin height and Fin width as shown in Figure 1.2. By increasing the channel width the drive current of the device can be increased.

Width of the Channel = 2×HF in + TF in (1.1)

Figure 1.1: FinFET Structure(Kawa, 2013)

FinFET can be used in two different modes: Shorted Gate (SG) mode and Indepen- dent Gate (IG) mode. In shorted gate mode both front and back gate are tied together while in independent mode both front and back gate are biased independently as shown in Figure 1.3.

Figure 1.2: FinFET Device (Raja and Madheswaran, 2013)

Figure 1.3: Shorted Gate and Independent Gate FinFET Structure (Mahor and Pat- tanaik, 2015)

The FinFET is a technology that is used within ICs due to its advantages like low power consumption, low operating voltage, high speed and reduced static leakage cur- rent. But it is not available as discrete devices. However FinFET technology is be- coming more widespread as feature sizes within integrated circuits fall and there is a growing need to provide very much higher levels of integration with less power con- sumption within integrated circuits.The main advantages of using FinFET technology are:

• Feature sizes: Possible to pass through the 20nm barrier previously thought as an end point.

• Power: Much lower power consumption allows high integration levels

• Operating voltage: FinFETs operate at a lower voltage.

• Operating speed Often in excess of 30% faster than the non-FinFET versions.

• Static leakage current: Typically reduced by up to 90%.

Therefore a new technique is proposed to design an low leakage SRAM cell which improves cell characteristics in hold, write and in read mode using FinFET technology.

1.3 OBJECTIVES OF THE PROJECT

The main objective of the project is to analyze the power, delay, and stability of a conventional 6T SRAM cell using FinFET technology and to implement an SRAM cell with a power reduction technique and also to analyze its power, delay and stability using FinFET.

1.4 CONVENTIONAL FINFET SRAM

Figure 1.4: FinFET SRAM

A conventional 6T SRAM using FinFET is shown in Figure 1.4. It has two inverters which are connected back to back (M1, M3, M2 and M4) and two access transistors (M5 and M6) that are connected to the bit lines, bit line (BL) and bit line bar (BLB). The access transistors provides access to internal nodes and the cross coupled inverters are used to store the two stable states i.e. zero and one. A SRAM cell has three operating modes namely write mode, hold mode and read mode (Bhadoria et al., 2016).

1.4.1 HOLD MODE

In hold or standby mode, a low voltage is given to the word line (i.e. WL=0) and the access transistors M6 and M5 are in off condition and therefore the access transistors

and the bitlines remains disconnected. In this mode the two inverters provide feedback as long as supply is provided and thus the data continues to remain in the latch condition.

1.4.2 READ MODE

In read mode, the bitlines are precharged to a high voltage level (i.e. VDD) and the word line is also enabled (i.e. WL=1) and thus the access transistors are connected to the bitlines and this allows transfer of values in the nodes (QB and Q) to bitlines. If the value at node Q is 1 then the bitline BLB gets discharged through the transistor M2 while the bitline BL remains at logical 1.

1.4.3 WRITE MODE

In write mode, the data to be written is given to the bitline BL and its complementary is n the given to the bitline BLB. Then the word line WL is asserted and the data will be written to the storage nodes. For the write ‘0’ operation the bitline BL is provided with a 0V while bitline BLB is pulled high to VDD and the word line is enabled.

1.5 STATIC NOISE MARGIN (SNM)

SNM is the measure of stability of the SRAM cell to hold its data against noise.SNM of SRAM is defined as minimum amount of noise voltage present on the storing nodes of SRAM required to flip the state of cell. There are two methods to measure the SNM of SRAM cell. First method is a graphical approach in which SNM can be obtained by drawing and mirroring the inverter characteristics and then finding the maximum possible square between them. The second approach involves the use of noise source voltages at the nodes. SNM Dependences includes cell ratio (CR), supply voltage and also pull up ratio (Shivaprakash and Suresh, 2016). Cell ratio is the ratio between sizes of the driver transistor to the load transistor during the read operation. Pull up ratio is the ratio between sizes of the load transistor to the access transistor during write operation. If the cell ratio increases, size of the driver transistor also increases, consequently increasing the current. As current increases, the speed of the SRAM cell also increases.

1.5.1 SRAM READ STABILITY

Data retention of the SRAM cell, both in standby mode and during a read access, is an important functional constraint in advanced technology nodes. The cell becomes less stable with lower supply voltage increasing leakage currents and increasing variability, all resulting from technology scaling (Geethumol and Sreekala, 2016). The stability is usually defined by the SNM as the maximum value of DC noise voltage that can be

tolerated by the SRAM cell without changing the stored bit.

Figure 1.5: Set Up for SNM Definition (Shivaprakash and Suresh, 2016)

In Figure 1.5, the equivalent circuit for the SNM definition is shown. The two DC noise voltage sources are placed in series with the cross-coupled inverters. The minimum value of noise voltage (Vn) which is necessary to flip the state of the cell is recorded as SNM. The graphical method to determine the SNM uses the static voltage transfer characteristics of the SRAM cell inverters. By superposing the voltage transfer characteristic (VTC) of one cell inverter to the inverse VTC of the other cell inverter the two-lobed graph is called a “butterfly” curve is obtained and it is used to determine the SNM. Its value is defined as the side length of the largest square that can be fitted inside the lobes of the “butterfly” curve. More the value of SNM, higher is the read stability of the SRAM cell. A cell with lower RSNM has poorer read stability (Mukherjee et al.,
2010).

1.5.2 SRAM WRITE STABILITY

Write margin is the measure of the ability to write data into the SRAM cell. Write margin voltage is the maximum noise voltage present at bit lines during successful write operation. When noise voltages exceeds the write margin voltage, then write failure occurs. The write SNM is measured using butterfly or VTC curves, which are obtained from a dc simulation sweeping the input of the inverters (QB and Q). For a successful write, only one cross point should be found on the butterfly curves, indicating that the cell is mono-stable (Sharma and Chopade, 2014). Write SNM for writing 1 is the width of the smallest square that can be embedded between the lower-right half of the curves. Write SNM for writing 0 can be obtained from a similar simulation. The final Write SNM for the cell is the minimum of the margin for writing 0 and writing 1. A cell with lower Write SNM has poorer write ability.

1.6 ORGANIZATION OF THE PROJECT

The overall thesis report is illustrated as follows: Chapter 2 includes literature survey of the project. In chapter 3, a SRAM cell with a power reduction technique is proposed and

its various operating modes are analyzed.The implementation of a 16 × 16 SRAM array is illustrated in Chapter 4. Simulation results and its analysis is explained in Chapter 5. Finally, conclusions are drawn in chapter 6.

1.7 SUMMARY OF THE PROJECT

Power issues due to short channel effects can be compensated by using the FinFET tech- nology. FinFET can be used to implement a SRAM cell with low power consumption and high stability.

CHAPTER 2
LITERATURE REVIEW

2.1 SRAM WITH POWER GATING TECHNIQUE

The technique is implemented using different states of the WL, BL, and BLB. Other than for read operation, one of the signals is always at low voltage level. This obser- vation is used to design a topology to reduce static and dynamic power. The technique is used to break the leakage path through ground for any low voltage level signals as shown in Figure 2.1. Word line, bit line and a complementary bit line are set to a high voltage level for the read operation and depending upon the data in the cell the bit lines get discharged or remain charge. During the write operation, word line and one of the bit lines are at high voltage and no need to discharge the bit lines. In hold state, both bit lines are at high voltage level but word line is at a lower voltage level and breaks the path between storage nodes and bit lines. This technique saves more static power dissipation. The reason for decrement in leakage current during write operation is sup- ply voltage and no path to ground. Either of bit line (BLB or BL) is at low logic during write operation or gives output =1, the connected PMOS is off which breaks the path to ground (Kumar et al., 2016). During read operation all the signal are at logic high and gives output=0, PMOS is ON and provide the path to discharge the one of the bit lines.

Figure 2.1: SRAM with Power Gating Technique (Kumar et al., 2016)

2.2 SRAM WITH CURRENT SHARING CONCEPT

The SRAM cell shown in Figure 2.2 consists of ten transistors with six main body transistors, similar to a conventional cell. The additional transistors are used to provide a reduction in the read path leakage and to power-gate the cell when it is in hold mode. The cell stability can be improved by using separate paths for write and read operations. The proposed cell operates in three modes: hold, write and read mode. The power gate transistor (MG) at the bottom of the main body is used to switch the cell between the active (i.e. read and write modes) and hold modes by adjusting the virtual ground voltage (VG). The HS signal controls the transistor MG. During active mode, VDD is applied to HS inorder to turn ON the transistor MG (Imani et al., 2015). Activating WWL or RWL signals enables the write and read operations respectively. The power gate transistor in the tail of the storage cell and sharing of current and read path are used to reduce the hold power, reshapes the butterfly diagram (higher read SNM stability) and acts as internal feedback to adaptively suppress the changes in the cell. In addition, this decreases the cell voltage drop in write and hold modes, improving write ability and significantly reducing the static power of cell.

Figure 2.2: SRAM with Current Sharing Concept (Imani et al., 2015)

2.3 8T SRAM

Due to a very high process variation and low noise margin of 6T SRAM, 8T-SRAM cell is used with separate lines for read and write. Stronger access transistors are required in order to improve write margin, while for improving read margin weaker access transis-

tors are needed. This issue can be resolved by separating read and write paths. Figure2.3 shows 8T SRAM cell structure. It consists of a 6T SRAM cell together with a read cir- cuit (R1- R2 transistors and RBL line). The write operation is done by BL and BLB lines through access transistors (AC1-AC2). R1 and R2 transistors are used in order to make the data stored in node Q on RBL line during read operation. Since most of SRAM cells are in standby mode, the leakage current is one of the main concerns for SRAM designs (Gopal et al., 2013). In order to reach the maximum density in SRAM memory, minimum width transistors are used. Minimum size transistors along with ac- curate sizing ratio of transistors requirements make SRAM cell reliability very sensitive to process variations. The effect of using FinFET and bulk CMOS transistors on power consumption and robustness of 6T and 8T SRAM cells are explored. Simulations are done using HSPICE with PTM models 22nm LP and 20nm LSTP for bulk CMOS and FinFET transistors respectively.Table 2.1 shows the value of SNM for the 8T SRAM.

Figure 2.3: 8T SRAM (Gopal et al., 2013) Table 2.1: SNM of 8T SRAM

Parameters CMOS FinFET RNM(mV) 358 379
WNM(mV) 210 344

2.4 7T SRAM ARRAY

There are seven transistors in this structure as shown Figure 2.4. It is similar to a 6T SRAM Cell and an additional NMOS transistor is placed between pull down transistors and ground node. Input of additional transistor NM5 is WL. Leakage currents mainly contribute sub threshold leakage and gate tunneling. Leakage power is depending on the storage of the cell. Sub threshold current flows when gate voltage of a transistor is

below the threshold voltage of transistor. In standby mode, when WL is asserted low, both access transistors (NM3 and NM4) are off. Due to the stored value (logic 0) in SRAM cell, sub threshold leakage current flows through off transistors. The additional bottom transistor NM5 is likely to cut off the ground path. Thus reduces the leakage paths through the SRAM cell sources. In active mode, when WL asserted high, bottom transistor NM5 turns ON (Bisht and Pranav, 2017). Thus read and write operations performed like 6T SRAM cell. Due to an additional transistor write access time is increased that is negligible. But there is an increase of size and for large arrays the size of array will be larger. Dimensional parameters of 7T SRAM cell are similar to
6T SRAM cell and the channel width of NM5 is 6m and channel length is 200nm is considered.

Table 2.2: Power of 7T SRAM Array

Parameters 7T SRAM 6T SRAM

Total power consumption(mW) 20.04 24.48

Figure 2.4: 7T SRAM (Bisht and Pranav, 2017)

The value of power obtained for the 16 × 16 SRAM array using 7T SRAM is shown in Table 2.2 and is compared with the power of array using 6T SRAM.By the use of FinFET Technology power and reliability issues in the SRAM cell can be reduced.By incorporating different control strategies the power consumption can be reduced to a large extent. One of the best method to reduce the power consumption is the use of sleep transistors and the stability of the cell can be increased by using separate bit lines for read and write operations.

CHAPTER 3
SRAM WITH POWER REDUCTION TECHNIQUE

The most commonly used SRAM structure is the 6T structure. In this case, both op- erations i.e. write and read make use of same path and this increases the probability of failures in read operation of SRAM cell. Therefore an improved way to reduce the effect of this problem is to use different paths for read operation and write operation. By the use of separate read path and write path the read path leakage is reduced which occurs through main loop and is also improves the read Static Noise Margin (SNM).

Figure 3.1: SRAM with Power Reduction Technique

SRAM with proposed reduction technique is shown in Figure 3.1. The proposed technique also has nine transistors of which six transistors forms the basic SRAM cell. The proposed cell also have three operating modes: write, hold and read. A sleep transistor N5 is used to control the sub threshold leakage. The transistor N5 will be in OFF condition for standby or hold mode while it will be in ON condition for the active mode i.e. for write and read mode.

3.1 DIFFERENT OPERATING MODES

3.1.1 READ MODE

In read mode the write word line WWL will be provided with a low voltage i.e. logic
0 and the read word line RWL will be provided with a high voltage i.e. logic 1. The control signal HS is also provided with a high voltage and the transistor N5 will be in ON condition. The read bit line RBL will be pre-charged to VDD. As the read word line is at logic one the data stored in the internal node can be read through the bit line RBL and depending on the data stored the bit line remains charged or gets discharged.

3.1.2 WRITE MODE

In write operation, the write word line WWL is at logic 1 and the read word line RWL will be at logic 0. The write operation is similar to that of basic 6T FinFET SRAM. The data to be written is given to the write bit line WBL and its complementary is given to the bit line WBLB. As the write word line is asserted the data will get written to the internal nodes. In this mode also the transistor N5 will be in ON condition as the control signal HS is at logic1.

3.1.3 HOLD MODE

The hold operation is also similar to that of basic 6T FinFET SRAM. In this mode both word -lines i.e. read word line and write word line will be at logic 0. Therefore the all the access transistors will be in OFF condition and the two cross-coupled inverters will be in latch condition as long supply is provided. The transistor N5 will be in OFF condition as the control signal HS is provided with logic 0 and this helps to reduce the leakage in standby mode.

Table 3.1: State of Sleep Transistor at Different Operational Modes

MODES WWL RWL HS N5
WRITE1 0 1 ON READ0 1 1 ON HOLD1 0 0 OFF

The status of sleep transistor N5 at different operations is shown in Table 3.1. From the table it is observed that the transistor N5 will be in OFF condition during hold mode while it is in ON condition for the active mode i.e. for read and write mode of SRAM. Thus this technique can be used to reduce the static power consumption of the cell and the proposed technique also improves the stability as different paths are used for read and write operation.

CHAPTER 4
16 × 16 SRAM ARRAY

The block diagram of the array of SRAM is shown in Figure 4.1.the main components includes the write driver, precharge circuit, sense amplifier, SRAM cell, row and column decoder and the sense amplifier. The SRAM cell is used to store data in form of binary zeros and ones. Number of SRAM cells is arranged in columns and rows in order to form an array.

Figure 4.1: Block Diagram of SRAM Architecture (Bisht and Pranav, 2017)

The 2N rows in the array are called word lines and the 2M columns in the array is known as bit lines. Thus there will be a total of 2(N + M) memory cells. Each column is provided with separate write drivers, sense amplifiers and precharge circuit in order to speed up the read and write operations (Bellerimath and Banakar, 2013).

4.1 PRECHARGE CIRCUIT

Figure 4.2: Precharge Circuit (Bisht and Pranav, 2017)

One of the essential components in a SRAM array is the precharge circuit. Precharged circuits are used to charge the bit lines to VDD. The circuit diagram for the precharge circuit is shown in Figure 4.2. The two transistors in the top are used for the purpose of precharging and the transistor PM0 is used for equalizing purpose in order to make sure that both the bit lines are at same potential before any operation.

4.2 WRITE DRIVER CIRCUIT

Write driver circuit performs the action of discharging any one of the bit lines. It is used to input data to be written to the bitlines and the write driver circuit is activated by enabling the Write Enable signal (WE). Each column needs one driver circuit only. The circuit diagram of write driver circuit is shown in Figure 4.3. It contains two inverters and four NMOS transistors.

Figure 4.3: Write driver circuit (Bisht and Pranav, 2017)

4.3 SENSE AMPLIFIER

Sense amplifier forms a major component of the array circuit. The circuit diagram of a sense amplifier is shown in Figure 4.4. Each column in the SRAM array is provided with a sense amplifier circuit. The main function of the sense amplifier is to identify the bit line difference and to validate the output correspondingly. It also helps to maintain read reliability and therefore it should be immune to the noise effects. In the considered differential type sense amplifier, the bit lines is considered as the inputs and the Sense Enable (SE) signal is used to activate the sense amplifier

Figure 4.4: Sense Amplifier (Bisht and Pranav, 2017)

4.4 ROW/COLUMN DECODER

In a SRAM array the column or row decoder is used to decode the address and to select the column and the row correspondingly. The control signal WE and WL is selected by using the column decoder and the row decoder. The block diagram of the decoder circuit is shown in Figure 4.5 and the circuit diagram using AND gates are shown in Figure 4.6. As a 4 to 16 decoder is used, it has four input lines and sixteen output lines. The truth table of the 4 to 16 decoder is shown in Table 4.1. It shows how the various rows or columns are selected in an SRAM array.

Figure 4.5: Block Diagram of Decoder (Bisht and Pranav, 2017)

Figure 4.6: Circuit Diagram of Decoder (Bisht and Pranav, 2017)

Table 4.1: Output Selection of the Decoder

Inputs Output Selection (As WL/WE Selection) A B C D
0 0 0 0 x0
0 0 0 1 x1
0 0 1 0 x2
0 0 1 1 x3
0 1 0 0 x4
0 1 0 1 x5
0 1 1 0 x6
0 1 1 1 x7
1 0 0 0 x8
1 0 0 1 x9
1 0 1 0 x10
1 0 1 1 x11
1 1 0 0 x12
1 1 0 1 x13
1 1 1 0 x14
1 1 1 1 x15

The implemented 16 × 16 SRAM array is used store 32 bytes of data. The array contains 16 write driver circuits, 16 precharge circuits and 16 sense amplifiers. Row and column decoder is used to select a particular WL and WE signal of write driver circuit depending on the cell to be used.

CHAPTER 5
RESULTS AND DISCUSSION

The proposed technique is simulated using HSPICE simulator at 20nm in FinFET tech- nology with 0.9V supply voltage. The different parameters that affects performance of a SRAM includes static noise margin (SNM), delay and power. The power and delay obtained for the SRAM cell with proposed reduction technique is shown in Table 5.1. The cell stability of a SRAM is characterized by the SNM value. The cell stability is affected by three types of noise margins: Read noise margin, write noise margin and hold noise margin. The SNM is obtained by drawing the VTC curve of an inverter and mirroring it and finding the maximum possible square between them as shown in Figure
5.1.

Figure 5.1: Butterfly Curve of a SRAM Cell (Manzoor et al., 2014) Table 5.1: Power and Delay of Proposed Technique

Parameters Read Write Hold

Power(µW ) 244.44 30.5 29.59

Delay(ps) 265.9 255.3 –

The read SNM thus obtained is shown in Figure 5.2. The stability is usually defined by the SNM as the maximum value of DC noise voltage that can be tolerated by the SRAM cell without changing the stored bit. The read SNM of proposed technique is obtained as 320mV.

Figure 5.2: Butterfly Curve for Read SNM

The write noise margin is obtained by initially setting the value of Q as zero and QB as one and then varying the bit line from one to zero respectively. Then the Q and QB is plotted and the point at which both intersect is noted. Using the proposed technique the write noise margin is obtained as 500mV. The plot obtained is shown in Figure 5.3. The hold SNM of proposed technique is also obtained by using the butterfly curve as shown in Figure 5.4 and it is obtained as 740mV.

Figure 5.3: Write Noise Margin

Figure 5.4: Butterfly Curve for Hold SNM

The read SNM obtained for the conventional 6T FinFET SRAM using the butterfly curve is shown in Figure 5.5 and the value is obtained as 200mV. The write noise margin for the conventional 6T FinFET SRAM is shown in the Figure 5.6 and its value is obtained as 400mV. The hold SNM for the conventional 6T FinFET SRAM is shown in Figure 5.7 and its value is obtained as 320mV.

Figure 5.5: Read Noise Margin of 6T SRAM

Figure 5.6: Write Noise Margin of 6T SRAM

Figure 5.7: Hold Noise Margin of 6T SRAM

The SNM of the proposed technique is compared with the conventional FinFET
6T SRAM and is shown in Table 5.2 and in Figure 5.8. It is observed that the read SNM is increased by 38% and the write and hold SNM is increased by 20% and 57% respectively when compared to conventional 6T FinFET SRAM.

Table 5.2: Comparison of SNM

Types Read SNM (mV) Write SNM (mV) Hold SNM (mV)

6T SRAM 200 400 320

Proposed Technique 320 500 740

Figure 5.8: Comparison of SNM

The delay of the proposed technique is compared with the conventional FinFET 6T SRAM and is shown in Table 5.3 and in Figure 5.9. It is observed that the read delay is reduced by 7% and the write delay is reduced by 9% when compared to conventional
6T FinFET SRAM.

Table 5.3: Comparison of Delay

Types 6T SRAM Proposed Technique

Read Delay (ps) 287. 36 265.9

Write Delay (ps) 280.13 255.3

Figure 5.9: Comparison of Delay

The power of the proposed technique is compared with the conventional FinFET
6T SRAM and is shown in Table 5.4 and in Figure 5.10. It is observed that the read power is reduced by 39% and the write and hold power is reduced by 81% and 62% respectively when compared to conventional 6T FinFET SRAM.

Table 5.4: Comparison of Static Power

Types Read Power (µW ) Write Power (µW ) Hold Power (µW )

6T SRAM 339.81 161.03 79.25

Proposed Technique 244.44 30.5 29.59

Figure 5.10: Comparison of Static Power

Variation of power with temperature is shown in Table 5.5 and in Figure 5.11 and it is seen that as temperature increases the power also increases as the leakage current increases with temperature.

Table 5.5: Variation of Power with Temperature

Temp Read Power (µW ) Write Power (µW ) Hold Power (µW )

50?C 32.96 252.223 31.26

100?C 34.035 278.480 32.73

150?C 35.437 295.683 33.40

Variation of power with threshold voltage is shown in Table 5.6 and in Figure 5.12 and it is seen that as the threshold voltage increases the sub threshold leakage decreases

and thus the power decreases. The power obtained for a 16 × 16 SRAM array is shown in Table 5.7 and in Figure 5.13.

Figure 5.11: Variation of Power with Temperature

Table 5.6: Variation of Power with Threshold Voltage (VT H )

VT H Read Power (µW ) Write Power (µW ) Hold Power (µW )

0.2 247.51 32.51 60.788

0.3 244.44 30.56 29.59

0.3 244.44 30.56 29.59

0.5 234.589 26.14 23.41

Figure 5.12: Variation of Power with Threshold Voltage

Table 5.7: Power of a 16 × 16 SRAM Array

Read Power (µW ) Write Power (µW ) Hold Power (µW )

333.02 244.31 244.31

Figure 5.13: Power of a 16 × 16 SRAM Array

The proposed technique is used to implement a 16 × 16 SRAM array and its power consumption is evaluated.The read power is obtained as 333.02µW and the write and hold power is obtained as 244.31W and 244.31µW respectively.

Figure 5.14: Comparison of Read Stability

Table 5.8: Comparison with Previous Works

Parameters (Zeinali et al., 2015) (Kumar et al., 2016) Proposed

Technology 14nm 32nm 20nm

Supply Voltage (V) 0.4 0.9 0.9

Read SNM (mV) 170.2 124 320

Write SNM (mV) – 363 500

Hold SNM (mV) 170.2 125 740

No. of Transistors 9 13 9

Figure 5.15: Comparison of Write Stability

Figure 5.16: Comparison of Hold Stability

The static noise margin of implemented the SRAM cell with reduction technique is compared with the previous works and its value is shown in Table 5.8.The comparison of read, write and hold noise margins with previous works are shown in Figure 5.14, Figure 5.15 and in Figure 5.16 respectively. It is observed that static noise margin of the implemented SRAM cell has been increased when compared to the previous works done.

CHAPTER 6
CONCLUSIONS

Scaling of conventional CMOS technology leads to an increase in short channel effects and leakage current. Therefore FinFET technology is used as a suitable replacement for the CMOS technology due to its low power consumption and low sub-threshold leakage. These devices increase the controllability of gate on channel with respect to CMOS transistors and suppress short channel effect. FinFET is used to implement a conventional 6T SRAM and a SRAM with power reduction technique and the analysis of power, delay and stability has been done. It is observed that when compared to conventional 6T SRAM cell, the proposed SRAM cell saves up to 39% of power in read operation and up to 81% of power in write operation and 62% of power in hold operation.The read delay of the proposed technique is reduced by 7% and the write delay is reduced by 9% when compared to conventional 6T FinFET SRAM. The read SNM of the proposed technique is increased by 38% and the write and hold SNM is increased by 20% and 57% respectively when compared to conventional 6T FinFET SRAM. A 16 × 16 SRAM array is also implemented using the proposed technique and the power is calculated using the Hspice software.

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LIST OF PUBLICATIONS

1. Jeny Elsa Joji, Sreekala K.S, Compensation Techniques for Low Power SRAM A Comparative Study. In National Conference on Recent Trends in Engineering Technology (NCRTET). Pathanamthitta,India, April 2017.

2. Jeny Elsa Joji, Sreekala K.S, Ashly John. (2018). FinFET Based Ultra Low
Power SRAM. International Journal of Engineering Research Technology (IJERT),
7(4), 226-229.

3. Jeny Elsa Joji, Sreekala K.S, Dhanusha P.B, Performance Analysis of CMOS and FinFET Based SRAM. In IEEE International Multi-Conference on Comput- ing, Communication, Electrical Nanotechnology (I2CN-2K18). Kottayam, India, April 2018.

4. Jeny Elsa Joji, Sreekala K.S, Hanna Mathew, Power and Read Delay Effi- cient Sensor Based Compensation Technique for Low Power SRAM. Third In- ternational Conference on Emerging Trends in Communication and Computing – ETCom 2018. Grenze Scientific Society, May 2018.(Accepted)